The present invention relates to a method for forming a self-aligned contact, and more particularly to a method for forming a self-aligned contact on a common source/drain region of transistors provided in a semicondutor substrate through high etching selectivity between a dielectric film and amorphous SiC, or high etching selectivity between a dielectric film and HexaChloroDisilane(HCD)-SiN.
During the process of manufacturing a semiconductor memory on a semiconductor chip, it is necessary to form a bit line contact hole or capacitor contact hole for exposing a source or drain region of a transistor in the semiconductor memory. subsequently, the bit line contact hole or capacitor contact hole is filled with a metal or polysilicon film to form a bit line contact or capacitor contact.
FIGS. 1(a) to 1(b) are cross-sectional views showing a conventional method for forming a contact hole. As shown in FIG. 1(a), a first transistor 10 and a second transistor 20 are formed in a common semiconductor substrate 1 by a conventional method of forming a semiconductor transistor such as a metal-oxide-semiconductor transistor. A common source/drain region 3 is provided between a first gate electrode 2a of the first transistor 10 and a second gate electrode 2b of the second transistor 20. Next, as a dielectric layer for covering the first transistor 10 and the second transistor 20, a thick silicon oxide film 5 is deposited thereon. In order to define a contact hole region 6xe2x80x2, a patterned photoresist film 7 is formed on the surface of the thick silicon oxide film 5 by the conventional process of photolithography. It should be noted that, in a horizontal direction, there must be a predetermined preventive distance 9 between the contact hole region 6xe2x80x2 and each of the first gate electrode 2a and the second gate electrode 2b. These preventive distances 9 can prevent the first gate electrode 2a and the second gate electrode 2b from being etched to become short when the thick silicon oxide film 5 is etched.
Referring to FIG. 1(b), using the patterned photoresist film 7 as a mask, the thick silicon oxide film 5 is etched to form a contact hole 8xe2x80x2 for exposing the common source/drain region 3 by a conventional process of anisotropic etching such as the process of reactive ion etching. After the formation of the contact hole 8xe2x80x2, the above-mentioned bit line contact or capacitor contact is formed by filling the contact hole 8xe2x80x2 with a conductive film (not shown).
As mentioned above, the predetermined preventive distance 9 is provided between the contact hole 8xe2x80x2 and each of the first gate electrode 2a and the second gate electrode 2b so as to prevent the first gate electrode 2a and the second gate electrode 2b from being etched to become short when the thick silicon oxide film 5 is etched. However, as to advanced high density semiconductor memory devices such as dynamic random access memory (DRAM) devices in the order of megabyte, it is necessary to achieve a very high integration of memory cells. In the prior art, the increase of the integration of the semiconductor memory devices is greatly restricted since the space between the first gate electrode 2a and the gate electrode 2b is lengthened by the preventive distance 9. During recent years, a self-aligned contact without the preventive distance 9 has been developed to increase the integration of the semiconductor memory devices. In other words, a self-aligned contact hole is substantially aligned with the common source/drain region 3 of the first transistor 10 and the second transistor 20. Furthermore, the size of the self-aligned contact hole is substantially larger than or equal to that of the common source/drain region 3. A conventional method for forming the self-aligned contact is described in the following with reference to FIGS. 2 to 5.
As shown in FIG. 2, an etching stopper layer 4 is deposited on the first transistor 10 and the second transistor 20 provided with the common source/drain region 3. Next, referring to FIG. 3, the etching stopper layer 4 is partially removed by a conventional process of anisotropic etching such as the process of reactive ion etching so as to form a first gate protection film 4a covering the first gate electrode 2a and a second gate protection film 4b covering the second gate electrode 2b. 
Referring to FIG. 4, a thick silicon oxide 5 is deposited on the first transistor 10 and the second transistor 20 to cover the first gate protection film 4a, the second gate protection film 4b, and the common source/drain region 3. In order to define a self-aligned contact region 6, a patterned photoresist film 7 is formed on the thick silicon oxide film 5 by a conventional process of photolithography. It should be noted that, unlike the structure shown in FIG. 1(a), there is no the above-mentioned preventive distance 9 between the self-aligned contact region 6 and each of the first gate electrode 4a and the second gate electrode 4b. As shown in FIG. 4, the size of the self-aligned contact region 6 is substantially larger than or equal to that of the common source/drain region 3. Furthermore, the self-aligned contact region 6 is substantially aligned with the common source/drain region 3.
Finally, referring to FIG. 5, using the patterned photoresist film 7 as a mask, the thick silicon oxide film 5 is etched to form a self-aligned contact hole 8 for exposing the common source/drain region 3 by a conventional process of anisotropic etching such as the process of reactive ion etching. After the formation of the self-aligned contact hole 8, the self-aligned bit line contact is formed by filling the self-aligned contact hole 8 with a conductive film (not shown).
In the above-mentioned method for forming a self-aligned contact, it is necessary to provide the first gate protection film 4a and the second gate protection film 4b for covering the first gate electrode 2a and the second gate electrode 2b, respectively. The reason is that the first gate protection film 4a and the second protection film 4b have a much slower etching rate than that of the thick silicon oxide film 5, so they prevent the first gate electrode 2a and the second gate electrode 2b from being etched, respectively, when the thick silicon oxide film 5 is etched. In the prior art, the first gate protection film 4a and the second gate protection film 4b are made of low pressure chemical vapor deposition-SiN (LPCVD-SiN) at a temperature of 450xc2x0 C. or above. During the RIE process using a reactive chemical gas containing C4F8 and CO, the etching selectivity of LPCVD-SiN to silicon oxide is 20, that is, the ratio of the etching rate of the silicon oxide to LPCVD-SiN is 20:1. The LPCVD-SiN is suitable for the gate protection film due to a high etching selectivity of LPCVD-SiN to silicon oxide. However, the dielectric constant (∈) of LPCVD-SiN is approximately 7.8, and therefore results in a large parasitic capacitance of the bit line formed by the self-aligned contact. Accordingly, the performance of the semiconductor memory device with the conventional self-aligned contact is deteriorated.
It is therefore an object of the present invention to provide a method for forming a self-aligned contact by using a gate protection film with a high etching selectivity to silicon oxide, thereby effectively preventing a gate electrode from being etched.
It is another object of the present invention to provide a method for forming a self-aligned contact by using a gate protection film with a low dielectric constant, thereby reducing the parasitic capacitance of a bit line contact.
A method for forming a self-aligned contact according to the present invention comprises the following steps. At the beginning, a gate protection film is formed to cover a gate electrode of a transistor provided in a semiconductor substrate. Next, a dielectric layer is deposited on the gate protection film. Finally, the dielectric layer is selectively etched to form a contact hole for exposing the source/drain region of the transistor. In the present invention, the gate protection film is made of amorphous SiC or HexaChloroDisilane-SiN (HCD-SiN).